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Open-source high-performance RISC-V processor
Scala 6.9k 867
Documentation for XiangShan
Markdown 432 151
Open-source high-performance non-blocking cache
Scala 93 41
Modern co-simulation framework for RISC-V CPUs
C++ 171 93
XiangShan Frontend Develop Environment
Shell 68 65
Super fast RISC-V ISA emulator for XiangShan processor
C 307 121
Open-source non-blocking L2 cache, used in XS-AI system
XSPdb is a Python-based extension of pdb designed for the XiangShan IP, providing GDB-like "interactive debugging" capabilities.
This repo includes XiangShan's function units
Documentation for XiangShan Design
