This repo consists of the iverilog implementation of a Parallel Prefix adder - 8bit (I/P - O/P). This was done as a part of a project Under UE19CS206 - Digital Design and Computer Organization Laboratory Course at PES University.
Parallel Prefix Adders achieve logarithmic time complexity by means of parallelizing the operation. For an n bit prefix adder, the critical path is one xor gate, one and/or gate and log(n) modules.
O(log k) Parallel FHE Conversion IP package featuring pipelined SystemVerilog RTL and Header-Only C++ Library. Designed to accelerate cryptographic pipelines by removing the sequential RNS bottleneck.
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