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Add CI and fix compile error#182

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lovyan03 merged 11 commits intom5stack:developfrom
lovyan03:develop
Feb 6, 2026
Merged

Add CI and fix compile error#182
lovyan03 merged 11 commits intom5stack:developfrom
lovyan03:develop

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@lovyan03 lovyan03 commented Feb 6, 2026

This pull request introduces comprehensive improvements to the build system and enhances compatibility across various ESP32 chip variants, including the new ESP32-H2. The main changes include the addition of CI workflows for Arduino and ESP-IDF builds, the introduction of a new build test example, and significant refactoring to support multiple ESP32 targets more robustly and maintainably.

Build System Enhancements:

  • Added GitHub Actions workflow .github/workflows/ArduinoBuild.yml to automatically build Arduino examples across a wide matrix of ESP32 and M5Stack boards and versions.
  • Added GitHub Actions workflow .github/workflows/IDFBuild.yml to build ESP-IDF-based examples for multiple ESP32 targets and IDF versions.

New Example for Build Testing:

  • Introduced the examples/Test/build_test directory with CMake and source files for both Arduino and ESP-IDF. This includes a comprehensive test sketch (main.cpp) that exercises a wide range of M5GFX drawing and display features, as well as relevant CMake configuration and SDK defaults. [1] [2] [3] [4] [5]

Platform Compatibility and Refactoring:

  • Refactored low-level ESP32 platform code to use C++ type traits and SFINAE for register access, improving compatibility and maintainability across ESP32 variants (including ESP32-H2), and reducing reliance on preprocessor conditionals. This affects GPIO, I2C, and DMA register access patterns. [1] [2] [3] [4] [5] [6] [7]
  • Added ESP32-H2 support in device headers and platform-specific source files, ensuring correct register access and peripheral handling for this new chip. [1] [2] [3] [4] [5] [6] [7]
  • Minor optimization for EPD panel DMA buffer blitting by adding -fomit-frame-pointer to the function's optimization flags.

lovyan03 and others added 11 commits January 5, 2026 15:58
compilation across ESP32/S3/C3/C6/H2/P4 targets with
Arduino-ESP32 v2/v3 and ESP-IDF v5.1/v5.3.
…d manager

- Remove M5Stack-specific board definitions (m5stack_core, m5stack_core2,
  m5stack_cores3) from Espressif package since M5GFX uses runtime detection
- Simplify matrix to SoC types only (ESP32, ESP32-S3, ESP32-C3, C6, P4, H2)
- Add M5Stack official board manager tests (M5Core, M5CoreS3) for
  compatibility verification with both v2.x and v3.x releases
- Make board_manager_url a matrix variable for flexibility

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
Use correct board IDs from boards.txt (m5stack_core, m5stack_cores3)
instead of display names from package index (M5Core, M5CoreS3).

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
…Panel_EPD

Synced from LovyanGFX develop (c13b7a5). Adds -fomit-frame-pointer to the
optimize attribute of blit_dmabuf() to prevent "a7 cannot be used in asm here"
error in ESP-IDF builds. See LovyanGFX#820.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
…upport

Replace version-based preprocessor detection (LGFX_GPIO_IN_SEL_CFG_REG)
with SFINAE type traits for GPIO func_in_sel_cfg/func_out_sel_cfg field
access. ESP-IDF renamed the struct fields from func_sel to in_sel/out_sel
in different patch versions per release branch (v5.1.7, v5.2.6, v5.3.4,
v5.4.2), making version-based detection unreliable. SFINAE detects the
actual struct layout at compile time, ensuring correct behavior across
all ESP-IDF versions and SoC targets.

Apply the same SFINAE approach for I2C bus_busy detection in Bus_I2C.cpp,
replacing chip-specific conditionals and i2c_ll dependency with compile-
time detection of status_reg vs sr member.

Add CONFIG_IDF_TARGET_ESP32H2 to GPIO single-bank access (common.hpp)
and I2C register access conditions (common.cpp).

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
…upport

Replace version-based preprocessor detection (LGFX_GPIO_IN_SEL_CFG_REG)
with SFINAE type traits for GPIO func_in_sel_cfg/func_out_sel_cfg field
access. ESP-IDF renamed the struct fields from func_sel to in_sel/out_sel
in different patch versions per release branch (v5.1.7, v5.2.6, v5.3.4,
v5.4.2), making version-based detection unreliable. SFINAE detects the
actual struct layout at compile time, ensuring correct behavior across
all ESP-IDF versions and SoC targets.

Apply the same SFINAE approach for I2C bus_busy detection in Bus_I2C.cpp,
replacing chip-specific conditionals with compile-time detection of
status_reg vs sr member.

Add CONFIG_IDF_TARGET_ESP32H2 to GPIO single-bank access (common.hpp)
and I2C register access conditions (common.cpp).

Add explicit ESP32-H2 branch in device.hpp to exclude Bus_Parallel8
(requires I2S, not available on H2). Guard soc/i2s_reg.h include with
__has_include in common.hpp for H2 compatibility.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
ESP32-H2's spi_reg.h defines SPI register macros (SPI_CMD_REG, SPI_W0_REG, etc.)
without parameters using undefined DR_REG_SPI_BASE, while the codebase uses them
with a port parameter like SPI_W0_REG(spi_port). Redefine the 7 affected macros
as parameterized versions using REG_SPI_BASE(i) to resolve compilation errors.

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
@lovyan03 lovyan03 merged commit 770e402 into m5stack:develop Feb 6, 2026
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