[RISCV] Implement "B" bit-manipulation extension and WCH vendor-proprietary "XW" extension#7859
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ArcaneNibble wants to merge 7 commits intoVector35:devfrom
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[RISCV] Implement "B" bit-manipulation extension and WCH vendor-proprietary "XW" extension#7859ArcaneNibble wants to merge 7 commits intoVector35:devfrom
ArcaneNibble wants to merge 7 commits intoVector35:devfrom
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These indicate to the linker that a relaxation _may_ be performed. This is an optimization which is not required. Silences log warnings.
These are single-bit bit-manipulation instructions.
These instructions assist with address-related computations.
These are "basic" bit-manipulation instructions which have a straightforward lifting to LLIL.
This includes a hardware-accelerated memory copy and custom compressed byte/halfword load/store instructions.
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This PR implements support for the RISC-V
Bbit manipulation instructions, which are broken up intoZba,Zbb, andZbssub-features.If acceptable for upstream, it also implements proprietary opcodes from Nanjing Qinheng Microelectronics which are used in their microcontroller products. This is currently not able to be auto-detected from
.riscv.attributesand must be manually selected.Also fixes #7809