Can't build base PDI: no run_post.tcl file found #51
Description
I just started working with @vysh55 on dcmac. I see that you've marked the commented out qsfp pins in the constraints file as fixed with the latest commit to the main branch. I cloned the latest main branch (commit: 4019f03) and tried to complete your deployment steps but got stuck on building the base pdi. Below I've included the entire terminal output from cloning the repository up to to the error in the build.py script. I appreciate your help thus far, and I hope you can tell me if I'm doing something wrong.
kif❱ git clone https://github.com/Xilinx/SLASH.git
Cloning into 'SLASH'...
remote: Enumerating objects: 2284, done.
remote: Counting objects: 100% (231/231), done.
remote: Compressing objects: 100% (74/74), done.
remote: Total 2284 (delta 189), reused 157 (delta 157), pack-reused 2053 (from 3)
Receiving objects: 100% (2284/2284), 3.40 MiB | 27.83 MiB/s, done.
Resolving deltas: 100% (1351/1351), done.
kif❱ cd SLASH/
kif(main)❱ git submodule update --init --recursive
Submodule 'submodules/qdma_drv' (https://github.com/Xilinx/dma_ip_drivers.git) registered for path 'submodules/qdma_drv'
Submodule 'submodules/v80-vitis-flow/submodules/aved' (https://github.com/Xilinx/AVED.git) registered for path 'submodules/v80-vitis-flow/submodules/aved'
Cloning into '/home/rsass/jaskin/main/SLASH/submodules/qdma_drv'...
Cloning into '/home/rsass/jaskin/main/SLASH/submodules/v80-vitis-flow/submodules/aved'...
Submodule path 'submodules/qdma_drv': checked out '03ac7f31e256c5604eeb970e98d343cf925ddb52'
Submodule path 'submodules/v80-vitis-flow/submodules/aved': checked out '7497599d2b452846515d7f2f22ad6bea2ebef522'
kif(main)❱ cd submodules/v80-vitis-flow/submodules/aved/
kif((amd_v80_gen5x8_24.1_20241002))❱ git apply ../../../../deploy/aved.patch
../../../../deploy/aved.patch:748: trailing whitespace.
../../../../deploy/aved.patch:1456: trailing whitespace.
../../../../deploy/aved.patch:1467: trailing whitespace.
../../../../deploy/aved.patch:1471: trailing whitespace.
../../../../deploy/aved.patch:1472: trailing whitespace.
warning: squelched 134 whitespace errors
warning: 139 lines add whitespace errors.
kif((amd_v80_gen5x8_24.1_20241002) *)❱ cd ../../../..
kif(main *)❱ cd deploy/base_pdi/
kif(main *)❱ python3 build.py --platform compute
--- Running Step 1: setup_step ---
mkdir -p /home/rsass/jaskin/main/SLASH/examples/05_perf/build
cp -r /home/rsass/jaskin/main/SLASH/submodules/v80-vitis-flow /home/rsass/jaskin/main/SLASH/examples/05_perf/build
--- Running Step 2: hls_step ---
Running HLS step
make -C /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls
make[1]: Entering directory '/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls'
if [ ! -d "build_perf.xcv80-lsva4737-2MHP-e-S" ]; then \
vitis_hls build.tcl -tclargs ip xcv80-lsva4737-2MHP-e-S perf; \
fi
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2024.2 (64-bit)
**** SW Build 5238294 on Nov 8 2024
**** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
**** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
**** Start of session at: Sat Jan 3 18:26:00 2026
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
source /opt/xilinx/Vitis/2024.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] For user 'rsass' on host 'kif' (Linux_x86_64 version 5.15.0-161-generic) on Sat Jan 03 18:26:02 EST 2026
INFO: [HLS 200-10] On os Ubuntu 22.04.5 LTS
INFO: [HLS 200-10] In directory '/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls'
WARNING: [HLS 200-2053] The vitis_hls executable is deprecated. Consider using vitis-run --mode hls --tcl
Sourcing Tcl script 'build.tcl'
INFO: [HLS 200-1510] Running: source build.tcl
INFO: [HLS 200-1510] Running: open_project build_perf.xcv80-lsva4737-2MHP-e-S
INFO: [HLS 200-10] Creating and opening project '/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S'.
INFO: [HLS 200-1510] Running: add_files perf.cpp -cflags -std=c++14
INFO: [HLS 200-10] Adding design file 'perf.cpp' to the project
INFO: [HLS 200-1510] Running: set_top perf
INFO: [HLS 200-1510] Running: open_solution sol1
INFO: [HLS 200-10] Creating and opening solution '/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1'.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.2%20English&url=ug1448-hls-guidance&resourceid=200-1505.html
INFO: [HLS 200-1510] Running: set_part xcv80-lsva4737-2MHP-e-S
WARNING: [HLS 200-655] The device family 'versalhbm-2MHP' is new to HLS - using 'versalaicore-2HP' characterization library
WARNING: [HLS 200-655] The device family 'versalhbm-2MHP' is new to HLS - using 'versalaicore-2HP' characterization library
INFO: [HLS 200-1611] Setting target device to 'xcv80-lsva4737-2MHP-e-S'
INFO: [HLS 200-1510] Running: create_clock -period 3.33 -name default
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.33ns.
INFO: [HLS 200-1510] Running: config_interface -m_axi_addr64=true
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0.04 seconds. CPU system time: 0.02 seconds. Elapsed time: 0.06 seconds; current allocated memory: 631.570 MB.
INFO: [HLS 200-10] Analyzing design file 'perf.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 1.7 seconds. CPU system time: 0.55 seconds. Elapsed time: 2.25 seconds; current allocated memory: 633.512 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
INFO: [HLS 200-1995] There were 64 instructions in the design after the 'Compile/Link' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 21 instructions in the design after the 'Unroll/Inline (step 1)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 16 instructions in the design after the 'Unroll/Inline (step 2)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 18 instructions in the design after the 'Unroll/Inline (step 3)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 18 instructions in the design after the 'Unroll/Inline (step 4)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 17 instructions in the design after the 'Array/Struct (step 1)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 17 instructions in the design after the 'Array/Struct (step 2)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 17 instructions in the design after the 'Array/Struct (step 3)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 17 instructions in the design after the 'Array/Struct (step 4)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 24 instructions in the design after the 'Array/Struct (step 5)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 24 instructions in the design after the 'Performance (step 1)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 24 instructions in the design after the 'Performance (step 2)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 24 instructions in the design after the 'Performance (step 3)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 24 instructions in the design after the 'Performance (step 4)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 29 instructions in the design after the 'HW Transforms (step 1)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 200-1995] There were 32 instructions in the design after the 'HW Transforms (step 2)' phase of compilation. See the Design Size Report for more details: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/syn/report/csynth_design_size.rpt
INFO: [HLS 214-188] Unrolling loop 'VITIS_LOOP_27_1' (perf.cpp:27:19) in function 'perf' partially with a factor of 2 (perf.cpp:23:0)
INFO: [HLS 214-115] Multiple burst writes of variable length and bit width 512 in loop 'VITIS_LOOP_27_1'(perf.cpp:27:19) has been inferred on bundle 'gmem0'. These burst requests might be further partitioned into multiple requests during RTL generation, based on max_read_burst_length or max_write_burst_length settings. (perf.cpp:27:19)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 1.48 seconds. CPU system time: 0.57 seconds. Elapsed time: 6.81 seconds; current allocated memory: 643.316 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 643.316 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 643.438 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 643.438 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.01 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.02 seconds; current allocated memory: 664.598 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 664.941 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'perf' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'perf_Pipeline_VITIS_LOOP_27_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_27_1'.
WARNING: [HLS 200-880] The II Violation in module 'perf_Pipeline_VITIS_LOOP_27_1' (loop 'VITIS_LOOP_27_1'): Unable to enforce a carried dependence constraint (II = 1, distance = 1, offset = 1) between bus write operation ('gmem0_addr_write_ln30', perf.cpp:30) on port 'gmem0' (perf.cpp:30) and bus write operation ('gmem0_addr_write_ln30', perf.cpp:30) on port 'gmem0' (perf.cpp:30).
Resolution: For help on HLS 200-880 see docs.xilinx.com/access/sources/dita/topic?Doc_Version=2024.2%20English&url=ug1448-hls-guidance&resourceid=200-880.html
INFO: [HLS 200-1470] Pipelining result : Target II = NA, Final II = 2, Depth = 3, loop 'VITIS_LOOP_27_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.44 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.47 seconds; current allocated memory: 665.902 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 665.902 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'perf'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.2 seconds. CPU system time: 0 seconds. Elapsed time: 0.19 seconds; current allocated memory: 665.902 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.14 seconds. CPU system time: 0 seconds. Elapsed time: 0.15 seconds; current allocated memory: 665.902 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'perf_Pipeline_VITIS_LOOP_27_1'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-1030] Apply Unified Pipeline Control on module 'perf_Pipeline_VITIS_LOOP_27_1' pipeline 'VITIS_LOOP_27_1' pipeline type 'loop pipeline'
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWVALID' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWADDR' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWID' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWLEN' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWSIZE' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWBURST' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWLOCK' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWCACHE' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWPROT' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWQOS' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWREGION' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_AWUSER' to 0.
WARNING: [RTGEN 206-101] Setting dangling out port 'perf_Pipeline_VITIS_LOOP_27_1/m_axi_gmem0_0_BREADY' to 0.
INFO: [RTGEN 206-100] Finished creating RTL model for 'perf_Pipeline_VITIS_LOOP_27_1'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.14 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.16 seconds; current allocated memory: 665.902 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'perf'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'perf/gmem0' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'perf/n' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on port 'perf/out_mem' to 's_axilite & ap_none'.
INFO: [RTGEN 206-500] Setting interface mode on function 'perf' to 's_axilite & ap_ctrl_hs'.
INFO: [RTGEN 206-100] Bundling port 'n', 'out_mem' to AXI-Lite port control.
INFO: [RTGEN 206-100] Finished creating RTL model for 'perf'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.22 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.23 seconds; current allocated memory: 665.902 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.58 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.59 seconds; current allocated memory: 668.164 MB.
INFO: [HLS 200-1603] Design has inferred MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-111] Finished Updating report files: CPU user time: 0.25 seconds. CPU system time: 0.03 seconds. Elapsed time: 0.27 seconds; current allocated memory: 672.766 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for perf.
INFO: [VLOG 209-307] Generating Verilog RTL for perf.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were NOT satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.37 MHz
INFO: [HLS 200-2161] Finished Command csynth_design Elapsed time: 00:00:11; Allocated memory: 41.195 MB.
INFO: [HLS 200-1510] Running: config_export -format ip_catalog
INFO: [HLS 200-1510] Running: export_design
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.
WARNING: /opt/xilinx/Vivado/2024.2/tps/lnx64/jre11.0.16_1 does not exist.
****** Vivado v2024.2 (64-bit)
**** SW Build 5239630 on Fri Nov 08 22:34:34 MST 2024
**** IP Build 5239520 on Sun Nov 10 16:12:51 MST 2024
**** SharedData Build 5239561 on Fri Nov 08 14:39:27 MST 2024
**** Start of session at: Sat Jan 3 18:26:16 2026
** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
** Copyright 2022-2024 Advanced Micro Devices, Inc. All Rights Reserved.
source run_ippack.tcl -notrace
INFO: calling package_hls_ip ip_types=vitis sysgen json_file=/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/sol1_data.json outdir=/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip srcdir=/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1 sort_interfaces_ports=false
INFO: Copied 1 ipmisc file(s) to /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/misc
INFO: Copied 5 verilog file(s) to /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/hdl/verilog
INFO: Copied 5 vhdl file(s) to /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/hdl/vhdl
INFO: Copied 10 swdriver file(s) to /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/drivers
INFO: Import ports from HDL: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/hdl/vhdl/perf.vhd (perf)
INFO: Add axi4lite interface s_axi_control
INFO: Add clock interface ap_clk
INFO: Add reset interface ap_rst_n
INFO: Add interrupt interface interrupt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/xilinx/Vivado/2024.2/data/ip'.
INFO: Add axi4full interface m_axi_gmem0
INFO: Calling post_process_vitis to specialize IP
INFO: Calling post_process_sysgen to specialize IP
Generating sysgen info xml from json file
INFO: Created IP /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/component.xml
INFO: Created IP archive /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls/build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/ip/xilinx_com_hls_perf_1_0.zip
INFO: [Common 17-206] Exiting Vivado at Sat Jan 3 18:26:23 2026...
INFO: [HLS 200-802] Generated output file build_perf.xcv80-lsva4737-2MHP-e-S/sol1/impl/export.zip
INFO: [HLS 200-2161] Finished Command export_design Elapsed time: 00:00:11; Allocated memory: 3.824 MB.
INFO: [HLS 200-112] Total CPU user time: 17.12 seconds. Total CPU system time: 2.34 seconds. Total elapsed time: 26.19 seconds; peak allocated memory: 676.590 MB.
make[1]: Leaving directory '/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/hls'
--- Running Step 3: linker_step ---
-- The C compiler identification is GNU 11.4.0
-- The CXX compiler identification is GNU 11.4.0
-- Detecting C compiler ABI info
-- Detecting C compiler ABI info - done
-- Check for working C compiler: /bin/cc - skipped
-- Detecting C compile features
-- Detecting C compile features - done
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Check for working CXX compiler: /bin/c++ - skipped
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- Configuring done
-- Generating done
-- Build files have been written to: /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/build/v80-vitis-flow/build
[ 5%] Building CXX object CMakeFiles/v80++-linker.dir/src/bd_builder/bd_builder.cpp.o
[ 11%] Building CXX object CMakeFiles/v80++-linker.dir/src/bd_builder/register.cpp.o
[ 16%] Building CXX object CMakeFiles/v80++-linker.dir/src/arg_parser/arg_parser.cpp.o
[ 22%] Building CXX object CMakeFiles/v80++-linker.dir/src/bd_builder/map_entry.cpp.o
[ 27%] Building CXX object CMakeFiles/v80++-linker.dir/src/bd_builder/system_map.cpp.o
[ 33%] Building CXX object CMakeFiles/v80++-linker.dir/src/main.cpp.o
[ 38%] Building CXX object CMakeFiles/v80++-linker.dir/src/sw_emu/arg.cpp.o
[ 44%] Building CXX object CMakeFiles/v80++-linker.dir/src/sw_emu/emulator.cpp.o
[ 50%] Building CXX object CMakeFiles/v80++-linker.dir/src/sw_emu/func.cpp.o
[ 55%] Building CXX object CMakeFiles/v80++-linker.dir/src/sw_emu/json_parser.cpp.o
[ 61%] Building CXX object CMakeFiles/v80++-linker.dir/src/sw_emu/zmq_client.cpp.o
[ 66%] Building CXX object CMakeFiles/v80++-linker.dir/src/utils/logger.cpp.o
[ 72%] Building CXX object CMakeFiles/v80++-linker.dir/src/xml_parser/area_estimates.cpp.o
/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/build/v80-vitis-flow/src/sw_emu/zmq_client.cpp: In member function ‘std::string ZmqClient::recv()’:
/home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/build/v80-vitis-flow/src/sw_emu/zmq_client.cpp:34:16: warning: ignoring return value of ‘zmq::recv_result_t zmq::detail::socket_base::recv(zmq::message_t&, zmq::recv_flags)’, declared with attribute ‘nodiscard’ [-Wunused-result]
34 | socket.recv(message, zmq::recv_flags::none);
| ~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/build/v80-vitis-flow/include/sw_emu/zmq_client.hpp:25,
from /home/rsass/jaskin/main/SLASH/deploy/base_pdi/deploy_project_compute/build/v80-vitis-flow/src/sw_emu/zmq_client.cpp:21:
/usr/include/zmq.hpp:1971:19: note: declared here
1971 | recv_result_t recv(message_t &msg, recv_flags flags = recv_flags::none)
| ^~~~
[ 77%] Building CXX object CMakeFiles/v80++-linker.dir/src/xml_parser/interface.cpp.o
[ 83%] Building CXX object CMakeFiles/v80++-linker.dir/src/xml_parser/kernel.cpp.o
[ 88%] Building CXX object CMakeFiles/v80++-linker.dir/src/xml_parser/resource.cpp.o
[ 94%] Building CXX object CMakeFiles/v80++-linker.dir/src/xml_parser/xml_parser.cpp.o
[100%] Linking CXX executable v80++-linker
[100%] Built target v80++-linker
Linker run completed.
Traceback (most recent call last):
File "/home/rsass/jaskin/main/SLASH/deploy/base_pdi/build.py", line 225, in <module>
main()
File "/home/rsass/jaskin/main/SLASH/deploy/base_pdi/build.py", line 187, in main
func(args.platform)
File "/home/rsass/jaskin/main/SLASH/deploy/base_pdi/build.py", line 106, in linker_step
shutil.copy(os.path.join(RESOURCES_PATH, "run_post.tcl"), AVED_SRC_DIR_COMPUTE)
File "/usr/lib/python3.10/shutil.py", line 417, in copy
copyfile(src, dst, follow_symlinks=follow_symlinks)
File "/usr/lib/python3.10/shutil.py", line 254, in copyfile
with open(src, 'rb') as fsrc:
FileNotFoundError: [Errno 2] No such file or directory: '/home/rsass/jaskin/main/SLASH/submodules/v80-vitis-flow/resources/run_post.tcl'